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74LVC373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
Product specification 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
FEATURES
* 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic * Supply voltage range of 2.7V to 3.6V * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * Direct interface with TTL levels * High impedance when VCC = 0V
DESCRIPTION
The 74LVC373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The '373' consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one setup time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The '373' is functionally identical to the '573', but the '573' has a different pin arrangement.
QUICK REFERENCE DATA
SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay Dn to Qn; LE to Qn Input capacitance Power dissipation capacitance per latch Notes 1 and 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL UNIT ns pF pF
4.2 4.6 5.0 20
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic Shrink Small Outline (SO) 20-Pin Plastic Shrink Small Outline (SSOP) Type II 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC373A D 74LVC373A DB 74LVC373A PW NORTH AMERICA 74LVC373A D 74LVC373A DB 7LVC373APW DH PKG. DWG. # SOT163-1 SOT339-1 SOT360-1
1998 Jul 29
2
853-1860 19802
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1
EN C1
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE
11
3 4 7 8 13 14 17 18
1D
2 5 6 9 12 15 16 19
GND 10
SA00383
SA00385
PIN DESCRIPTION
PIN NUMBER 1 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 11 10 20 SYMBOL OE D0-D7 Q0-Q7 LE GND VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Latch enable input (active-High) Ground (0V) Positive supply voltage
FUNCTIONAL DIAGRAM
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7 LE OE LATCH 1 to 8 3-State OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
LOGIC SYMBOL
11 3 4 7 8 13 14 17 18 1
SA00387
D0 D1 D2 D3 D4 D5 D6 D7 11 1 LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9
12 15 16
19
SA00384
1998 Jul 29
3
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
SA00386
FUNCTION TABLE
INPUTS
OPERATING MODES
OUTPUTS Dn L H l h l h INTERNAL LATCHES L H L H L H Q0 to Q7 L H H H Z Z
OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs H h L l X Z L L L L H H
LE H H L L L L
= HIGH voltage level = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition = Don't care = High impedance OFF-state
1998 Jul 29
4
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC Input voltage range DC Output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 -40 0 0 MAX 3.6 V 3.6 5.5 VCC 5.5 +85 20 10 C ns/V V V UNIT
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +6.5 "50 -0.5 to VCC +0.5 -0.5 to 6.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 29
5
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ Ioff ICC ICC Input leakage current2 VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND VCC = 0.0V; VI or VO = 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 "0 1 0.1 0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 "10 "10 10 500 A A A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
3-State output OFF-state current Power off leakage supply Quiescent supply current Additional quiescent supply current per input pin
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
1998 Jul 29
6
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ tW tSU th PARAMETER Propagation delay Dn to Qn Propagation delay LE to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn LE pulse width HIGH Setup time Dn to LE Hold time Dn to LE WAVEFORM VCC = 3.3V 0.3V MIN 1, 5 2, 5 3, 5 3, 5 2 4 4 1.5 1.5 1.5 1.5 3.0 2.0 1.5 TYP1 4.2 4.6 4.8 4.3 1.5 0 0.3 MAX 6.8 7.2 7.7 6.1 - - - VCC = 2.7V MIN 1.5 1.5 1.5 1.5 3.0 2.0 1.5 MAX 7.8 8.2 8.7 7.1 - - - VCC = 1.2V TYP 19 21 22 15 - - - ns ns ns ns ns ns ns UNIT
NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25C.
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH -0.3V at VCC w 2.7V; VY = VOH - 0.1 VCC at VCC t 2.7V
VI INPUT GND VOH OUTPUT VOL tPHL tPLH VM VCC Qn OUTPUT LOW-to-OFF OFF-to-LOW VX VM VOL tPHZ tPZH VM VI nOE INPUT GND VM
tPLZ
tPZL
SY00041
VOH Qn OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM
Waveform 1. Input (Dn) to output (Qn) propagation delays.
VI LE INPUT
GND
outputs disabled
outputs enabled
VM
SW00207
tw tPHL VM
Waveform 3. 3-State enable and disable times.
tPLH
VOH Qn OUTPUT VOL
SA00388
Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays
1998 Jul 29
7
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
AC WAVEFORMS
with 5-volt tolerant inputs/outputs VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH -0.3V at VCC w 2.7V; VY = VOH - 0.1 VCC at VCC t 2.7V
Dn INPUT
TEST CIRCUIT
VCC S1 2GND
LE INPUT GND
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 4. Data setup and hold times for the Dn input to the LE input. (The shaded areas indicate when the input is permitted to change for predictable output performance).
1998 Jul 29
EEE E EEEEEEEEEE EEE EEEEEEEE EEE
VM th th tSU tSU VI VM
VI
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH SWITCH Open 2SW00073
DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SW00047
Waveform 5. Load circuitry for switching times.
8
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1998 Jul 29
9
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1998 Jul 29
10
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1998 Jul 29
11
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC373A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98 9397-750-04506
Philips Semiconductors
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